1. Technical Field
The present disclosure relates to transmission channels.
The disclosure relates, but not exclusively, to transmission channels for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
Sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internistic, surgical and radiological field.
The ultrasounds normally used are, for example, between 2 and 20 MHz in frequency. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.
These ultrasounds are being normally generated by a piezoceramic crystal inserted in a probe maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination). The same probe is able to collect a return signal or echo, which may be suitably processed by a computer and displayed on a monitor.
The ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the reflected percentage conveys information about the impedance difference between the crossed tissues. It is to be noted that, the big impedance difference between a bone and a tissue being considered, with the sonography it is generally not possible to see behind a bone, which causes a total reflection of the ultrasounds, while air or gas zones give “shade”, causing a partial reflection of the ultrasounds.
The time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the crossed tissues (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).
Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, may essentially comprise three parts:                a probe comprising at least one transducer, for example of the ultrasonic type, which transmits and receives an ultrasound signal;        an electronic system that drives the transducer for the generation of the ultrasound signal or pulse to be transmitted and receives an echo signal of return at the probe of this pulse, processing in consequence the received echo signal; and        a displaying system of a corresponding sonography image processed based on the echo signal received by the probe.        
The word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals. In a broad sense, a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed, for example by men or by other machines. Many transducers are both sensors and actuators. An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse.
A typical transmission channel or TX channel being used in these applications is schematically shown in FIG. 1.
The transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUSIN, a level shifter 3, in turn connected to a high voltage buffer block 4. The high voltage buffer block 4 is electrically coupled between pairs of high voltage reference terminals, respectively higher voltage reference terminals HVP0 and HVP1 and lower voltage reference terminals HVM0 and HVM1, and has a pair of input terminals, INB1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB1 and OUTB2, connected to a corresponding pair of input terminals, INC1 and INC2 of a clamping block 5.
Furthermore, the clamping block 5 is connected to a clamp voltage reference terminal PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1, in turn connected, through an anti-noise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.
A high voltage switch 7 is electrically coupled between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1. This high voltage switch 7 is able to transmit an output signal being at the output of the anti-noise block 6 to the second output terminal LVout during the receiving step of the transmission channel 1.
It is to be noted that the switch 7 may be a high voltage one since, during the transmission step of the transmission channel 1, a signal being on the connection terminal Xdcr is a high voltage signal although the switch 7 is off. When this switch 7 is instead on, i.e., during the reception step of the transmission channel 1, the signal Xdcr is generally at a voltage value next to zero since the piezoelectric transducer connected to the transmission channel 1 is sensing small return echoes of ultrasound pulse signals, as shown in FIG. 2.
Typically, an ultrasonic transducer transmits a high voltage pulse of the duration of a few us, and listens for reception of the echo of this pulse, generated by the reflection on the organs of a subject under examination, for the duration of about 250 us, to go back to the transmission of a new high voltage pulse.
For example, a first pulse IM1 and a second pulse IM2 are transmitted with a peak to peak excursion equal, in the example shown, to 190 Vpp with reception by the transducer of corresponding echoes shown in FIG. 2 and indicated with E1 and E2.
The high voltage switch 7 is shown in greater detail in FIG. 3A, while its equivalent circuit according to working conditions (ON) is shown in FIG. 3B.
The high voltage switch 7 comprises a first switching transistor MS1 and a second switching transistor MS2, being electrically coupled, in series to each other, between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 and having respective control or gate terminals connected, at the turning-on of the switch 7 itself, to a first and to a second supply voltage reference terminals, VDD_M and VDD_P respectively. FIG. 3A also shows the equivalent diodes, DS1 and DS2, of the switching transistors, MS1 and MS2, as well as their gate-source capacitances, Cg1 and Cg2 respectively.
The first capacitance Cg1 of the first switching transistor MS1 is connected between the corresponding gate terminal, in turn connected to the first supply voltage reference terminal VDD_M and a first switching node XS1, corresponding to a source terminal of the first switching transistor MS1. Similarly, the second capacitance Cg2 of the second switching transistor MS2 is connected between the relative gate terminal, in turn connected to the second supply voltage reference terminal VDD_P and a second switching node XS2, corresponding to a source terminal of the second switching transistor MS2.
As shown in the equivalent circuit of FIG. 3B, when the high voltage switch 7 is on and thus the gate terminals of the switching transistors MS1 and MS2 are connected to the first VDD_M and to the second supply voltage reference terminal VDD_P as indicated in FIG. 3A (which in FIG. 3B, for sake of simplicity, have been shown as a single reference voltage, for example, ground, being these first and second supply voltage references), these switching transistors behave as respective resistances R1 and R2, that are electrically coupled between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 (the second output terminal LVout coinciding with the second switching node XS2) and interconnected in correspondence with the first switching node XS1.
According to these conditions, the first capacitance Cg1 is connected between the first connection node XS1 and the first supply voltage reference VDD_M, while the second capacitance Cg2 is connected between the second connection node XS2 and the second supply voltage reference VDD_P. The first and second supply voltage references are fixed supplies, and are shown for sake of simplicity in FIG. 3B as a single reference voltage, the ground GND. This parallel capacitance introduces a strong mitigation of the signal at the input of the high voltage switch 7, i.e., of the signal at the output of the transmission channel 1 after the anti-noise block 6.
In general, then, the switch 7 should be a high voltage one so as not to break itself during the transmission step but it is in practice on always with low voltages during the receiving step.
Further, the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB1 and a first buffer diode DB1, being electrically coupled, in series to each other, between a first higher voltage reference terminal HVP0 and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, electrically coupled, in series to each other, between the buffer central node XBc and a first lower voltage reference terminal HVM0. The first and second buffer transistors, MB1 and MB2, have respective control or gate terminals in correspondence with a first XB1 and with a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first DRB1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and second input terminals, INB1 and INB2, of the high voltage buffer block 4.
The high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, being electrically coupled, in series to each other, between a second higher voltage reference terminal HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, electrically coupled, in series to each other, between the buffer central node XBc and a second lower voltage reference terminal HVM1. The third and fourth buffer transistors, MB3 and MB4, have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB1 and to the second inner circuit node XB2 and then to the first DRB1 and to the second buffer input driver DRB2, respectively, as well as to a first OUTB1 and to a second output terminal OUTB2.
In the example of the figure, the first and third buffer transistors, MB1 and MB3, are high voltage P-channel MOS transistors (HV Pmos) while the second and fourth buffer transistors, MB2 and MB4, are high voltage N-channel MOS transistors (HV Nmos). Moreover, the buffer diodes, DB1, DB2, DB3 and DB4, are high voltage diodes (HV diode).
The clamping block 5 has in turn a first INC1 and a second input terminal INC2, respectively connected to the first OUTB1 and second output terminal OUTB2 of the high voltage buffer block 4.
The clamping block 5 comprises a first clamp driver DRC1 connected between the first input terminal INC1 and a control or gate terminal of a first clamp transistor MC1, in turn electrically coupled, in series with a first clamp diode DC1, between the clamp voltage reference terminal PGND, for example a ground, and a clamp central node XCc. The first clamp transistor MC1 and the first clamp diode DC1 are interconnected in correspondence with a first clamp circuit node XC1.
The clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn electrically coupled, in series with a second clamp diode DC2, between the clamp central node XCc and the clamp voltage reference terminal PGND. The second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2.
The clamp central node XCc is also connected to the first output terminal HVout of the transmission channel 1, in turn connected to the connection terminal Xdcr through an anti-noise block 6 comprising respective first and second anti-noise diodes, DN1 and DN2, connected in antiparallel, i.e., by having the anode terminal of the first diode connected to the cathode terminal of the second diode and vice versa, between the first output terminal HVout and the connection terminal Xdcr.
In the example of the figure, the first clamp transistor MC1 is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the clamp diodes, DC1 and DC2, are high voltage diodes (HV diode) while the anti-noise diodes, DN1 and DN2, are low voltage diodes (LV diode).
The clamping block 5 is also shown in FIG. 4, in the case of a clamping operation to a ground voltage reference GND, i.e., during the receiving step of the transmission channel 1. It is to be noted that the clamping to the ground voltage reference GND generally should be ensured also when the load is mainly capacitive. In this case, the output terminal of the transmission channel should generally be brought back to this ground value after the transmission.
Furthermore, the clamping to the ground is generally desirable in applications in which the high voltage wave form to be transmitted, besides oscillating between a positive value of high voltage and a negative value of high voltage, stays for determined periods of time at the ground value.
Also the anti-noise block 6 is indicated too, being connected between the first output terminal HVout and the connection terminal Xdcr of the transmission channel 1.
This FIG. 4 also shows the equivalent diodes, DMC1 and DMC2, of the clamp transistors, MC1 and MC2, respectively, the first and second clamp input drivers, DRC1 and DRC2, being connected between a first clamp supply voltage reference terminal and a second clamp supply voltage reference terminal, higher VDD_P and lower VDD_M, respectively, and the ground GND, whereto also the clamp central node XCc is connected.